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<title>PACKSSWB/PACKSSDW—Pack with Signed Saturation </title></head>
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<h1>PACKSSWB/PACKSSDW—Pack with Signed Saturation</h1>
<table>
<tr>
<th>CPUID Feature Flag</th>
<th>Description</th>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th></tr>
<tr>
<td>MMX</td>
<td>Converts 4 packed signed word integers from <em>mm1</em> and from <em>mm2/m64 </em>into 8 packed signed byte integers in <em>mm1 </em>using<em> </em>signed saturation<em>.</em></td>
<td>
<p>0F 63 /r<sup>1</sup></p>
<p>PACKSSWB <em>mm1, mm2/m64</em></p></td>
<td>RM</td>
<td>V/V</td></tr>
<tr>
<td>SSE2</td>
<td>Converts 8 packed signed word integers from <em>xmm1</em> and from <em>xxm2/m128</em> into 16 packed signed byte integers in <em>xxm1 </em>using<em> </em>signed saturation.</td>
<td>
<p>66 0F 63 /<em>r</em></p>
<p>PACKSSWB <em>xmm1, xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td></tr>
<tr>
<td>MMX</td>
<td>Converts 2 packed signed doubleword integers from <em>mm1</em> and from <em>mm2/m64</em> into 4 packed signed word integers in <em>mm1 </em>using signed saturation.</td>
<td>
<p>0F 6B /<em>r</em><sup>1</sup></p>
<p>PACKSSDW <em>mm1, mm2/m64</em></p></td>
<td>RM</td>
<td>V/V</td></tr>
<tr>
<td>SSE2</td>
<td>Converts 4 packed signed doubleword integers from <em>xmm1</em> and from <em>xxm2/m128 </em>into 8 packed signed word integers in <em>xxm1 </em>using<em> </em>signed saturation.</td>
<td>
<p>66 0F 6B /<em>r</em></p>
<p>PACKSSDW <em>xmm1, xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td></tr>
<tr>
<td>AVX</td>
<td>Converts 8 packed signed word integers from <em>xmm2</em> and from <em>xmm3/m128</em> into 16 packed signed byte integers in <em>xmm1</em> using signed saturation.</td>
<td>
<p>VEX.NDS.128.66.0F.WIG 63 /r</p>
<p>VPACKSSWB <em>xmm1,xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td></tr>
<tr>
<td>AVX</td>
<td>Converts 4 packed signed doubleword integers from <em>xmm2 </em>and from <em>xmm3/m128 </em>into 8 packed signed word integers in<em> xmm1 </em>using signed saturation.</td>
<td>
<p>VEX.NDS.128.66.0F.WIG 6B /r</p>
<p>VPACKSSDW<em> xmm1,xmm2, xmm3/m128</em></p></td>
<td>RVM</td>
<td>V/V</td></tr>
<tr>
<td>AVX2</td>
<td>Converts 16 packed signed word integers from <em>ymm2</em> and from <em>ymm3/m256</em> into 32 packed signed byte integers in <em>ymm1 </em>using signed saturation.</td>
<td>
<p>VEX.NDS.256.66.0F.WIG 63 /r</p>
<p>VPACKSSWB <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td></tr>
<tr>
<td>AVX2</td>
<td>Converts 8 packed signed doubleword integers from <em>ymm2</em> and from <em>ymm3/m256 </em>into 16 packed signed word integers in <em>ymm1</em>using<em> </em>signed saturation.</td>
<td>
<p>VEX.NDS.256.66.0F.WIG 6B /r</p>
<p>VPACKSSDW <em>ymm1, ymm2, ymm3/m256</em></p></td>
<td>RVM</td>
<td>V/V</td></tr>
<tr>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p></td>
<td>Converts packed signed word integers from <em>xmm2</em> and from <em>xmm3/m128</em> into packed signed byte integers in <em>xmm1 </em>using<em> </em>signed saturation under writemask k1.</td>
<td>
<p>EVEX.NDS.128.66.0F.WIG 63 /<em>r</em></p>
<p>VPACKSSWB <em>xmm1 {k1}{z}, xmm2, xmm3/m128</em></p></td>
<td>FVM</td>
<td>V/V</td></tr>
<tr>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p></td>
<td>Converts packed signed word integers from <em>ymm2</em> and from <em>ymm3/m256</em> into packed signed byte integers in <em>ymm1 </em>using<em> </em>signed saturation under writemask k1.</td>
<td>
<p>EVEX.NDS.256.66.0F.WIG 63 /<em>r</em></p>
<p>VPACKSSWB <em>ymm1 {k1}{z}, ymm2, ymm3/m256</em></p></td>
<td>FVM</td>
<td>V/V</td></tr>
<tr>
<td>AVX512BW</td>
<td>Converts packed signed word integers from <em>zmm2</em> and from <em>zmm3/m512</em> into packed signed byte integers in <em>zmm1 </em>using<em> </em>signed saturation under writemask k1.</td>
<td>
<p>EVEX.NDS.512.66.0F.WIG 63 /<em>r</em></p>
<p>VPACKSSWB <em>zmm1 {k1}{z}, zmm2, zmm3/m512</em></p></td>
<td>FVM</td>
<td>V/V</td></tr>
<tr>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p></td>
<td>Converts packed signed doubleword integers from <em>xmm2</em> and from xmm3/m128/m32bcst into packed signed word integers in xmm1 using<em> </em>signed saturation under writemask k1.</td>
<td>
<p>EVEX.NDS.128.66.0F.W0 6B /<em>r</em></p>
<p>VPACKSSDW xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td></tr></table>
<table>
<tr>
<td>
<p>EVEX.NDS.256.66.0F.W0 6B /r</p>
<p>VPACKSSDW ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512BW</p></td>
<td>Converts packed signed doubleword integers from <em>ymm2</em> and from ymm3/m256/m32bcst into packed signed word integers in ymm1 using<em> </em>signed saturation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F.W0 6B /r</p>
<p>VPACKSSDW zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512BW</td>
<td>Converts packed signed doubleword integers from zmm2 and from zmm3/m512/m32bcst into packed signed word integers in zmm1 using<em> </em>signed saturation under writemask k1.</td></tr></table>
<p>NOTES:</p>
<p>1. See note in Section 2.4, “AVX and SSE Instruction Exception Specification” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A</em> and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers” in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A</em>.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FVM</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Converts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-tions. See Figure 4-6 for an example of the packing operation.</p>
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<h3>Figure 4-6.  Operation of the PACKSSDW Instruction Using 64-bit Operands</h3>
<p>PACKSSWB converts packed signed word integers in the first and second source operands into packed signed byte integers using signed saturation to handle overflow conditions beyond the range of signed byte integers. If the signed doubleword value is beyond the range of an unsigned word (i.e. greater than 7FH or less than 80H), the saturated signed byte integer value of 7FH or 80H, respectively, is stored in the destination. PACKSSDW converts packed signed doubleword integers in the first and second source operands into packed signed word integers using signed saturation to handle overflow conditions beyond 7FFFH and 8000H.</p>
<p>EVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the writemask k1.</p>
<p>EVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the writemask k1.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.</p>
<p>VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM destination register destination are unmodified.</p>
<p><strong>Operation</strong></p>
<p><strong>PACKSSWB instruction (128-bit Legacy SSE version)</strong></p>
<p>DEST[7:0] (cid:197) SaturateSignedWordToSignedByte (DEST[15:0]);</p>
<p>DEST[15:8] (cid:197) SaturateSignedWordToSignedByte (DEST[31:16]);</p>
<p>DEST[23:16] (cid:197) SaturateSignedWordToSignedByte (DEST[47:32]);</p>
<p>DEST[31:24] (cid:197) SaturateSignedWordToSignedByte (DEST[63:48]);</p>
<p>DEST[39:32] (cid:197) SaturateSignedWordToSignedByte (DEST[79:64]);</p>
<p>DEST[47:40] (cid:197) SaturateSignedWordToSignedByte (DEST[95:80]);</p>
<p>DEST[55:48] (cid:197) SaturateSignedWordToSignedByte (DEST[111:96]);</p>
<p>DEST[63:56] (cid:197) SaturateSignedWordToSignedByte (DEST[127:112]);</p>
<p>DEST[71:64] (cid:197) SaturateSignedWordToSignedByte (SRC[15:0]);</p>
<p>DEST[79:72] (cid:197) SaturateSignedWordToSignedByte (SRC[31:16]);</p>
<p>DEST[87:80] (cid:197) SaturateSignedWordToSignedByte (SRC[47:32]);</p>
<p>DEST[95:88] (cid:197) SaturateSignedWordToSignedByte (SRC[63:48]);</p>
<p>DEST[103:96] (cid:197) SaturateSignedWordToSignedByte (SRC[79:64]);</p>
<p>DEST[111:104] (cid:197) SaturateSignedWordToSignedByte (SRC[95:80]);</p>
<p>DEST[119:112] (cid:197) SaturateSignedWordToSignedByte (SRC[111:96]);</p>
<p>DEST[127:120] (cid:197) SaturateSignedWordToSignedByte (SRC[127:112]);</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>PACKSSDW instruction (128-bit Legacy SSE version)</strong></p>
<p>DEST[15:0] (cid:197) SaturateSignedDwordToSignedWord (DEST[31:0]);</p>
<p>DEST[31:16] (cid:197) SaturateSignedDwordToSignedWord (DEST[63:32]);</p>
<p>DEST[47:32] (cid:197) SaturateSignedDwordToSignedWord (DEST[95:64]);</p>
<p>DEST[63:48] (cid:197) SaturateSignedDwordToSignedWord (DEST[127:96]);</p>
<p>DEST[79:64] (cid:197) SaturateSignedDwordToSignedWord (SRC[31:0]);</p>
<p>DEST[95:80] (cid:197) SaturateSignedDwordToSignedWord (SRC[63:32]);</p>
<p>DEST[111:96] (cid:197) SaturateSignedDwordToSignedWord (SRC[95:64]);</p>
<p>DEST[127:112] (cid:197) SaturateSignedDwordToSignedWord (SRC[127:96]);</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>VPACKSSWB instruction (VEX.128 encoded version)</strong></p>
<p>DEST[7:0] (cid:197) SaturateSignedWordToSignedByte (SRC1[15:0]);</p>
<p>DEST[15:8] (cid:197) SaturateSignedWordToSignedByte (SRC1[31:16]);</p>
<p>DEST[23:16] (cid:197) SaturateSignedWordToSignedByte (SRC1[47:32]);</p>
<p>DEST[31:24] (cid:197) SaturateSignedWordToSignedByte (SRC1[63:48]);</p>
<p>DEST[39:32] (cid:197) SaturateSignedWordToSignedByte (SRC1[79:64]);</p>
<p>DEST[47:40] (cid:197) SaturateSignedWordToSignedByte (SRC1[95:80]);</p>
<p>DEST[55:48] (cid:197) SaturateSignedWordToSignedByte (SRC1[111:96]);</p>
<p>DEST[63:56] (cid:197) SaturateSignedWordToSignedByte (SRC1[127:112]);</p>
<p>DEST[71:64] (cid:197) SaturateSignedWordToSignedByte (SRC2[15:0]);</p>
<p>DEST[79:72] (cid:197) SaturateSignedWordToSignedByte (SRC2[31:16]);</p>
<p>DEST[87:80] (cid:197) SaturateSignedWordToSignedByte (SRC2[47:32]);</p>
<p>DEST[95:88] (cid:197) SaturateSignedWordToSignedByte (SRC2[63:48]);</p>
<p>DEST[103:96] (cid:197) SaturateSignedWordToSignedByte (SRC2[79:64]);</p>
<p>DEST[111:104] (cid:197) SaturateSignedWordToSignedByte (SRC2[95:80]);</p>
<p>DEST[119:112] (cid:197) SaturateSignedWordToSignedByte (SRC2[111:96]);</p>
<p>DEST[127:120] (cid:197) SaturateSignedWordToSignedByte (SRC2[127:112]);</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0;</p>
<p><strong>VPACKSSDW instruction (VEX.128 encoded version)</strong></p>
<p>DEST[15:0] (cid:197) SaturateSignedDwordToSignedWord (SRC1[31:0]);</p>
<p>DEST[31:16] (cid:197) SaturateSignedDwordToSignedWord (SRC1[63:32]);</p>
<p>DEST[47:32] (cid:197) SaturateSignedDwordToSignedWord (SRC1[95:64]);</p>
<p>DEST[63:48] (cid:197) SaturateSignedDwordToSignedWord (SRC1[127:96]);</p>
<p>DEST[79:64] (cid:197) SaturateSignedDwordToSignedWord (SRC2[31:0]);</p>
<p>DEST[95:80] (cid:197) SaturateSignedDwordToSignedWord (SRC2[63:32]);</p>
<p>DEST[111:96] (cid:197) SaturateSignedDwordToSignedWord (SRC2[95:64]);</p>
<p>DEST[127:112] (cid:197) SaturateSignedDwordToSignedWord (SRC2[127:96]);</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0;</p>
<p><strong>VPACKSSWB instruction (VEX.256 encoded version)</strong></p>
<p>DEST[7:0] (cid:197) SaturateSignedWordToSignedByte (SRC1[15:0]);</p>
<p>DEST[15:8] (cid:197) SaturateSignedWordToSignedByte (SRC1[31:16]);</p>
<p>DEST[23:16] (cid:197) SaturateSignedWordToSignedByte (SRC1[47:32]);</p>
<p>DEST[31:24] (cid:197) SaturateSignedWordToSignedByte (SRC1[63:48]);</p>
<p>DEST[39:32] (cid:197) SaturateSignedWordToSignedByte (SRC1[79:64]);</p>
<p>DEST[47:40] (cid:197) SaturateSignedWordToSignedByte (SRC1[95:80]);</p>
<p>DEST[55:48] (cid:197) SaturateSignedWordToSignedByte (SRC1[111:96]);</p>
<p>DEST[63:56] (cid:197) SaturateSignedWordToSignedByte (SRC1[127:112]);</p>
<p>DEST[71:64] (cid:197) SaturateSignedWordToSignedByte (SRC2[15:0]);</p>
<p>DEST[79:72] (cid:197) SaturateSignedWordToSignedByte (SRC2[31:16]);</p>
<p>DEST[87:80] (cid:197) SaturateSignedWordToSignedByte (SRC2[47:32]);</p>
<p>DEST[95:88] (cid:197) SaturateSignedWordToSignedByte (SRC2[63:48]);</p>
<p>DEST[103:96] (cid:197) SaturateSignedWordToSignedByte (SRC2[79:64]);</p>
<p>DEST[111:104] (cid:197) SaturateSignedWordToSignedByte (SRC2[95:80]);</p>
<p>DEST[119:112] (cid:197) SaturateSignedWordToSignedByte (SRC2[111:96]);</p>
<p>DEST[127:120] (cid:197) SaturateSignedWordToSignedByte (SRC2[127:112]);</p>
<p>DEST[135:128] (cid:197) SaturateSignedWordToSignedByte (SRC1[143:128]);</p>
<p>DEST[143:136] (cid:197) SaturateSignedWordToSignedByte (SRC1[159:144]);</p>
<p>DEST[151:144] (cid:197) SaturateSignedWordToSignedByte (SRC1[175:160]);</p>
<p>DEST[159:152] (cid:197) SaturateSignedWordToSignedByte (SRC1[191:176]);</p>
<p>DEST[167:160] (cid:197) SaturateSignedWordToSignedByte (SRC1[207:192]);</p>
<p>DEST[175:168] (cid:197) SaturateSignedWordToSignedByte (SRC1[223:208]);</p>
<p>DEST[183:176] (cid:197) SaturateSignedWordToSignedByte (SRC1[239:224]);</p>
<p>DEST[191:184] (cid:197) SaturateSignedWordToSignedByte (SRC1[255:240]);</p>
<p>DEST[199:192] (cid:197) SaturateSignedWordToSignedByte (SRC2[143:128]);</p>
<p>DEST[207:200] (cid:197) SaturateSignedWordToSignedByte (SRC2[159:144]);</p>
<p>DEST[215:208] (cid:197) SaturateSignedWordToSignedByte (SRC2[175:160]);</p>
<p>DEST[223:216] (cid:197) SaturateSignedWordToSignedByte (SRC2[191:176]);</p>
<p>DEST[231:224] (cid:197) SaturateSignedWordToSignedByte (SRC2[207:192]);</p>
<p>DEST[239:232] (cid:197) SaturateSignedWordToSignedByte (SRC2[223:208]);</p>
<p>DEST[247:240] (cid:197) SaturateSignedWordToSignedByte (SRC2[239:224]);</p>
<p>DEST[255:248] (cid:197) SaturateSignedWordToSignedByte (SRC2[255:240]);</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0;</p>
<p><strong>VPACKSSDW instruction (VEX.256 encoded version)</strong></p>
<p>DEST[15:0] (cid:197) SaturateSignedDwordToSignedWord (SRC1[31:0]);</p>
<p>DEST[31:16] (cid:197) SaturateSignedDwordToSignedWord (SRC1[63:32]);</p>
<p>DEST[47:32] (cid:197) SaturateSignedDwordToSignedWord (SRC1[95:64]);</p>
<p>DEST[63:48] (cid:197) SaturateSignedDwordToSignedWord (SRC1[127:96]);</p>
<p>DEST[79:64] (cid:197) SaturateSignedDwordToSignedWord (SRC2[31:0]);</p>
<p>DEST[95:80] (cid:197) SaturateSignedDwordToSignedWord (SRC2[63:32]);</p>
<p>DEST[111:96] (cid:197) SaturateSignedDwordToSignedWord (SRC2[95:64]);</p>
<p>DEST[127:112] (cid:197) SaturateSignedDwordToSignedWord (SRC2[127:96]);</p>
<p>DEST[143:128] (cid:197) SaturateSignedDwordToSignedWord (SRC1[159:128]);</p>
<p>DEST[159:144] (cid:197) SaturateSignedDwordToSignedWord (SRC1[191:160]);</p>
<p>DEST[175:160] (cid:197) SaturateSignedDwordToSignedWord (SRC1[223:192]);</p>
<p>DEST[191:176] (cid:197) SaturateSignedDwordToSignedWord (SRC1[255:224]);</p>
<p>DEST[207:192] (cid:197) SaturateSignedDwordToSignedWord (SRC2[159:128]);</p>
<p>DEST[223:208] (cid:197) SaturateSignedDwordToSignedWord (SRC2[191:160]);</p>
<p>DEST[239:224] (cid:197) SaturateSignedDwordToSignedWord (SRC2[223:192]);</p>
<p>DEST[255:240] (cid:197) SaturateSignedDwordToSignedWord (SRC2[255:224]);</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0;</p>
<p><strong>VPACKSSWB (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (16, 128), (32, 256), (64, 512)</p>
<p>TMP_DEST[7:0] (cid:197) SaturateSignedWordToSignedByte (SRC1[15:0]);</p>
<p>TMP_DEST[15:8] (cid:197) SaturateSignedWordToSignedByte (SRC1[31:16]);</p>
<p>TMP_DEST[23:16] (cid:197) SaturateSignedWordToSignedByte (SRC1[47:32]);</p>
<p>TMP_DEST[31:24] (cid:197) SaturateSignedWordToSignedByte (SRC1[63:48]);</p>
<p>TMP_DEST[39:32] (cid:197) SaturateSignedWordToSignedByte (SRC1[79:64]);</p>
<p>TMP_DEST[47:40] (cid:197) SaturateSignedWordToSignedByte (SRC1[95:80]);</p>
<p>TMP_DEST[55:48] (cid:197) SaturateSignedWordToSignedByte (SRC1[111:96]);</p>
<p>TMP_DEST[63:56] (cid:197) SaturateSignedWordToSignedByte (SRC1[127:112]);</p>
<p>TMP_DEST[71:64] (cid:197) SaturateSignedWordToSignedByte (SRC2[15:0]);</p>
<p>TMP_DEST[79:72] (cid:197) SaturateSignedWordToSignedByte (SRC2[31:16]);</p>
<p>TMP_DEST[87:80] (cid:197) SaturateSignedWordToSignedByte (SRC2[47:32]);</p>
<p>TMP_DEST[95:88] (cid:197) SaturateSignedWordToSignedByte (SRC2[63:48]);</p>
<p>TMP_DEST[103:96] (cid:197) SaturateSignedWordToSignedByte (SRC2[79:64]);</p>
<p>TMP_DEST[111:104] (cid:197) SaturateSignedWordToSignedByte (SRC2[95:80]);</p>
<p>TMP_DEST[119:112] (cid:197) SaturateSignedWordToSignedByte (SRC2[111:96]);</p>
<p>TMP_DEST[127:120] (cid:197) SaturateSignedWordToSignedByte (SRC2[127:112]);</p>
<p>IF VL &gt;= 256</p>
<p>TMP_DEST[135:128](cid:197) SaturateSignedWordToSignedByte (SRC1[143:128]);</p>
<p>TMP_DEST[143:136] (cid:197) SaturateSignedWordToSignedByte (SRC1[159:144]);</p>
<p>TMP_DEST[151:144] (cid:197) SaturateSignedWordToSignedByte (SRC1[175:160]);</p>
<p>TMP_DEST[159:152] (cid:197) SaturateSignedWordToSignedByte (SRC1[191:176]);</p>
<p>TMP_DEST[167:160] (cid:197) SaturateSignedWordToSignedByte (SRC1[207:192]);</p>
<p>TMP_DEST[175:168] (cid:197) SaturateSignedWordToSignedByte (SRC1[223:208]);</p>
<p>TMP_DEST[183:176] (cid:197) SaturateSignedWordToSignedByte (SRC1[239:224]);</p>
<p>TMP_DEST[191:184] (cid:197) SaturateSignedWordToSignedByte (SRC1[255:240]);</p>
<p>TMP_DEST[199:192] (cid:197) SaturateSignedWordToSignedByte (SRC2[143:128]);</p>
<p>TMP_DEST[207:200] (cid:197) SaturateSignedWordToSignedByte (SRC2[159:144]);</p>
<p>TMP_DEST[215:208] (cid:197) SaturateSignedWordToSignedByte (SRC2[175:160]);</p>
<p>TMP_DEST[223:216] (cid:197) SaturateSignedWordToSignedByte (SRC2[191:176]);</p>
<p>TMP_DEST[231:224] (cid:197) SaturateSignedWordToSignedByte (SRC2[207:192]);</p>
<p>TMP_DEST[239:232] (cid:197) SaturateSignedWordToSignedByte (SRC2[223:208]);</p>
<p>TMP_DEST[247:240] (cid:197) SaturateSignedWordToSignedByte (SRC2[239:224]);</p>
<p>TMP_DEST[255:248] (cid:197) SaturateSignedWordToSignedByte (SRC2[255:240]);</p>
<p>FI;</p>
<p>IF VL &gt;= 512</p>
<p>TMP_DEST[263:256] (cid:197) SaturateSignedWordToSignedByte (SRC1[271:256]);</p>
<p>TMP_DEST[271:264] (cid:197) SaturateSignedWordToSignedByte (SRC1[287:272]);</p>
<p>TMP_DEST[279:272] (cid:197) SaturateSignedWordToSignedByte (SRC1[303:288]);</p>
<p>TMP_DEST[287:280] (cid:197) SaturateSignedWordToSignedByte (SRC1[319:304]);</p>
<p>TMP_DEST[295:288] (cid:197) SaturateSignedWordToSignedByte (SRC1[335:320]);</p>
<p>TMP_DEST[303:296] (cid:197) SaturateSignedWordToSignedByte (SRC1[351:336]);</p>
<p>TMP_DEST[311:304] (cid:197) SaturateSignedWordToSignedByte (SRC1[367:352]);</p>
<p>TMP_DEST[319:312] (cid:197) SaturateSignedWordToSignedByte (SRC1[383:368]);</p>
<p>TMP_DEST[327:320] (cid:197) SaturateSignedWordToSignedByte (SRC2[271:256]);</p>
<p>TMP_DEST[335:328] (cid:197) SaturateSignedWordToSignedByte (SRC2[287:272]);</p>
<p>TMP_DEST[343:336] (cid:197) SaturateSignedWordToSignedByte (SRC2[303:288]);</p>
<p>TMP_DEST[351:344] (cid:197) SaturateSignedWordToSignedByte (SRC2[319:304]);</p>
<p>TMP_DEST[359:352] (cid:197) SaturateSignedWordToSignedByte (SRC2[335:320]);</p>
<p>TMP_DEST[367:360] (cid:197) SaturateSignedWordToSignedByte (SRC2[351:336]);</p>
<p>TMP_DEST[375:368] (cid:197) SaturateSignedWordToSignedByte (SRC2[367:352]);</p>
<p>TMP_DEST[383:376] (cid:197) SaturateSignedWordToSignedByte (SRC2[383:368]);</p>
<p>TMP_DEST[391:384] (cid:197) SaturateSignedWordToSignedByte (SRC1[399:384]);</p>
<p>TMP_DEST[399:392] (cid:197) SaturateSignedWordToSignedByte (SRC1[415:400]);</p>
<p>TMP_DEST[407:400] (cid:197) SaturateSignedWordToSignedByte (SRC1[431:416]);</p>
<p>TMP_DEST[415:408] (cid:197) SaturateSignedWordToSignedByte (SRC1[447:432]);</p>
<p>TMP_DEST[423:416] (cid:197) SaturateSignedWordToSignedByte (SRC1[463:448]);</p>
<p>TMP_DEST[431:424] (cid:197) SaturateSignedWordToSignedByte (SRC1[479:464]);</p>
<p>TMP_DEST[439:432] (cid:197) SaturateSignedWordToSignedByte (SRC1[495:480]);</p>
<p>TMP_DEST[447:440] (cid:197) SaturateSignedWordToSignedByte (SRC1[511:496]);</p>
<p>TMP_DEST[455:448] (cid:197) SaturateSignedWordToSignedByte (SRC2[399:384]);</p>
<p>TMP_DEST[463:456] (cid:197) SaturateSignedWordToSignedByte (SRC2[415:400]);</p>
<p>TMP_DEST[471:464] (cid:197) SaturateSignedWordToSignedByte (SRC2[431:416]);</p>
<p>TMP_DEST[479:472] (cid:197) SaturateSignedWordToSignedByte (SRC2[447:432]);</p>
<p>TMP_DEST[487:480] (cid:197) SaturateSignedWordToSignedByte (SRC2[463:448]);</p>
<p>TMP_DEST[495:488] (cid:197) SaturateSignedWordToSignedByte (SRC2[479:464]);</p>
<p>TMP_DEST[503:496] (cid:197) SaturateSignedWordToSignedByte (SRC2[495:480]);</p>
<p>TMP_DEST[511:504] (cid:197) SaturateSignedWordToSignedByte (SRC2[511:496]);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 8</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>DEST[i+7:i] (cid:197) TMP_DEST[i+7:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+7:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+7:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VPACKSSDW (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (8, 128), (16, 256), (32, 512)</p>
<p>FOR j (cid:197) 0 TO ((KL/2) - 1)</p>
<p>i (cid:197) j * 32</p>
<p>IF (EVEX.b == 1) AND (SRC2 *is memory*)</p>
<p>THEN</p>
<p>TMP_SRC2[i+31:i] (cid:197) SRC2[31:0]</p>
<p>ELSE</p>
<p>TMP_SRC2[i+31:i] (cid:197) SRC2[i+31:i]</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>TMP_DEST[15:0] (cid:197) SaturateSignedDwordToSignedWord (SRC1[31:0]);</p>
<p>TMP_DEST[31:16] (cid:197) SaturateSignedDwordToSignedWord (SRC1[63:32]);</p>
<p>TMP_DEST[47:32] (cid:197) SaturateSignedDwordToSignedWord (SRC1[95:64]);</p>
<p>TMP_DEST[63:48] (cid:197) SaturateSignedDwordToSignedWord (SRC1[127:96]);</p>
<p>TMP_DEST[79:64] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[31:0]);</p>
<p>TMP_DEST[95:80] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[63:32]);</p>
<p>TMP_DEST[111:96] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[95:64]);</p>
<p>TMP_DEST[127:112] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[127:96]);</p>
<p>IF VL &gt;= 256</p>
<p>TMP_DEST[143:128] (cid:197) SaturateSignedDwordToSignedWord (SRC1[159:128]);</p>
<p>TMP_DEST[159:144] (cid:197) SaturateSignedDwordToSignedWord (SRC1[191:160]);</p>
<p>TMP_DEST[175:160] (cid:197) SaturateSignedDwordToSignedWord (SRC1[223:192]);</p>
<p>TMP_DEST[191:176] (cid:197) SaturateSignedDwordToSignedWord (SRC1[255:224]);</p>
<p>TMP_DEST[207:192] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[159:128]);</p>
<p>TMP_DEST[223:208] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[191:160]);</p>
<p>TMP_DEST[239:224] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[223:192]);</p>
<p>TMP_DEST[255:240] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[255:224]);</p>
<p>FI;</p>
<p>IF VL &gt;= 512</p>
<p>TMP_DEST[271:256] (cid:197) SaturateSignedDwordToSignedWord (SRC1[287:256]);</p>
<p>TMP_DEST[287:272] (cid:197) SaturateSignedDwordToSignedWord (SRC1[319:288]);</p>
<p>TMP_DEST[303:288] (cid:197) SaturateSignedDwordToSignedWord (SRC1[351:320]);</p>
<p>TMP_DEST[319:304] (cid:197) SaturateSignedDwordToSignedWord (SRC1[383:352]);</p>
<p>TMP_DEST[335:320] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[287:256]);</p>
<p>TMP_DEST[351:336] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[319:288]);</p>
<p>TMP_DEST[367:352] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[351:320]);</p>
<p>TMP_DEST[383:368] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[383:352]);</p>
<p>TMP_DEST[399:384] (cid:197) SaturateSignedDwordToSignedWord (SRC1[415:384]);</p>
<p>TMP_DEST[415:400] (cid:197) SaturateSignedDwordToSignedWord (SRC1[447:416]);</p>
<p>TMP_DEST[431:416] (cid:197) SaturateSignedDwordToSignedWord (SRC1[479:448]);</p>
<p>TMP_DEST[447:432] (cid:197) SaturateSignedDwordToSignedWord (SRC1[511:480]);</p>
<p>TMP_DEST[463:448] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[415:384]);</p>
<p>TMP_DEST[479:464] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[447:416]);</p>
<p>TMP_DEST[495:480] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[479:448]);</p>
<p>TMP_DEST[511:496] (cid:197) SaturateSignedDwordToSignedWord (TMP_SRC2[511:480]);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 16</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+15:i] (cid:197) TMP_DEST[i+15:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+15:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+15:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalents</strong></p>
<p>VPACKSSDW__m512i _mm512_packs_epi32(__m512i m1, __m512i m2);</p>
<p>VPACKSSDW__m512i _mm512_mask_packs_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);</p>
<p>VPACKSSDW__m512i _mm512_maskz_packs_epi32( __mmask32 k, __m512i m1, __m512i m2);</p>
<p>VPACKSSDW__m256i _mm256_mask_packs_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);</p>
<p>VPACKSSDW__m256i _mm256_maskz_packs_epi32( __mmask16 k, __m256i m1, __m256i m2);</p>
<p>VPACKSSDW__m128i _mm_mask_packs_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);</p>
<p>VPACKSSDW__m128i _mm_maskz_packs_epi32( __mmask8 k, __m128i m1, __m128i m2);</p>
<p>VPACKSSWB__m512i _mm512_packs_epi16(__m512i m1, __m512i m2);</p>
<p>VPACKSSWB__m512i _mm512_mask_packs_epi16(__m512i s, __mmask32 k, __m512i m1, __m512i m2);</p>
<p>VPACKSSWB__m512i _mm512_maskz_packs_epi16( __mmask32 k, __m512i m1, __m512i m2);</p>
<p>VPACKSSWB__m256i _mm256_mask_packs_epi16( __m256i s, __mmask16 k, __m256i m1, __m256i m2);</p>
<p>VPACKSSWB__m256i _mm256_maskz_packs_epi16( __mmask16 k, __m256i m1, __m256i m2);</p>
<p>VPACKSSWB__m128i _mm_mask_packs_epi16( __m128i s, __mmask8 k, __m128i m1, __m128i m2);</p>
<p>VPACKSSWB__m128i _mm_maskz_packs_epi16( __mmask8 k, __m128i m1, __m128i m2);</p>
<p>PACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)</p>
<p>PACKSSDW __m128i _mm_packs_epi32(__m128i m1, __m128i m2)</p>
<p>VPACKSSWB __m256i _mm256_packs_epi16(__m256i m1, __m256i m2)</p>
<p>VPACKSSDW __m256i _mm256_packs_epi32(__m256i m1, __m256i m2)</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<table class="exception-table">
<tr>
<td>EVEX-encoded VPACKSSDW, see Exceptions Type E4NF.</td></tr>
<tr>
<td>EVEX-encoded VPACKSSWB, see Exceptions Type E4NF.nb.</td></tr></table></body></html>